1. Field of the Invention
The invention relates generally to machine readable media having a design structure that embodies integrated circuit architectures (i.e., designs), related integrated circuit structures and instructions for fabrication thereof. More particularly, the invention relates to a data structure comprising enhanced performance integrated circuit architectures, related integrated circuit structures and instructions for fabrication thereof.
2. Description of the Related Art
Modern semiconductor circuits often integrate circuit types or components, such as transistors, resistors and capacitors, for which different types of performance characteristics are desirably optimized. For example, field effect transistors that are used within logic circuits may desirably be optimized to provide enhanced integrated circuit speed. In comparison, storage capacitors used in dynamic memory circuits may alternatively be optimized to provide enhanced charge storage capacity.
The optimization of performance characteristics of various semiconductor circuits and semiconductor devices often leads to competing processing requirements. Thus, a need exists for integrated circuit designs and resulting structures that efficiently allow for optimization of various integrated circuit and device types.
Semiconductor structures, and methods for fabrication thereof, that include individually optimized devices and components are known in the semiconductor fabrication art. For example, Chan et al., in U.S. Pat. No. 6,821,826, teaches a three-dimensional complementary metal oxide semiconductor (CMOS) structure having separate field effect transistor (FET) devices fabricated upon different crystallographic orientation semiconductor substrates. The different crystallographic orientations provide for optimization of charge carrier mobility within the separate field effect transistors.
Semiconductor circuit fabrication is certain to continue to require enhanced levels of performance and optimization of various semiconductor circuits and devices within reduced semiconductor substrate surface area. Thus, integrated circuit and semiconductor architectures, structures and methods for fabrication thereof that provide for such ready optimization are desirable.